ace9020 is a vhf oscillator, up-converter and prescaler. it is used in an offset modulated transmit architecture where a uhf synthesiser makes the channel selection and a second synthesiser generates a fixed transmit offset. a vco signal drives a buffer in ace9020 to feed an on- chip prescaler and transmit up-converter. the prescaler is a dual two-modulus divider and drives the main synthesiser input of the ace9030. the ssb up-converter suppresses the unwanted transmit sideband. the vhf oscillator is buffered to drive the auxiliary synthesiser input of the ace9030 and is locked to the offset frequency. this frequency is modulated by varying the resonant frequency of the external tank circuit. both this oscillator and the uhf vco drive the up-converting mixer to generate the transmit signal. various power saving modes for battery economy are included. these allow the transmit sections to be shut down during stand-by and the whole chip can be shut down during sleep mode. the circuit techniques used have been chosen to minimise external components and at the same time give very high performance. features ? low power low voltage (3.6 to 5.0 v) operation ? power down modes ? differential signals to minimise cross-talk ? auxiliary oscillator with transmit up-converter ? prescaler for main synthesiser ? part of the ace integrated cellular phone chipset ? small outline 28 pin package applications ? amps and tacs cellular telephone ? two-way radio systems related products ace9020 is part of the following chipset: ? ace9030 radio interface and twin synthesiser ? ace9040 audio processor ? ace9050 system controller and data modem absolute maximum ratings supply voltage 6v storage temperature - 65 cto+150 c operating temperature - 30 cto+85 c voltage at any pin -0.3v to v cc +0.3v static sensitivity (hbm) min 500v figure 2 - ace9020 simplified block digram ace9020 receiver and transmitter interface figure 1 - pin connections - top view pd1 pd2 gnd bias_ref vcc_tx txpa+ txpa- rset_txpa gnd_txosc tank+ tank- vcc_div gnd_osc mod_cntrl div_out+ div_out- ratio_sel gnd_div txosc+ txosc- vcc_txosc gnd_rx rxvcoin n.c. vcc_rx n.c. n.c. vcc 128 14 15 note: pin 1 is identified by moulded spot and by coding orientation. np28 ace9020 vhf osc rset_txpa tank+ tank- txosc+ txosc- txpa+ txpa- bias & power down control bias_ref pd1 pd2 rxvcoin div_out+ div_out- ratio_sel mod_cntrl divide by 64/65 or 128/129 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copy right 1997 -200 6 , zarlink semiconductor inc. all rights reserved. ordering information ace9020b/kg/np1s 28 pin ssop tubes ace9020b/kg/np1t 28 pin ssop tape & reel ace9020b/kg/np2p 28 pin ssop* tubes, bake & drypack ace9020b/kg/np2q 28 pin ssop* tape & reel, bake & drypack *pb free matte tin may 2006
2 ace9020 pin no. name type description 1 pd1 i power down control input 1 2 pd2 i power down control input 2 3 gnd supply ground 4 bias_ref i reference current for bias control 5 vcc_tx supply transmit section supply voltage 6 txpa+ o transmit up-converter open collector output 7 txpa- o transmit up-converter open collector output 8 rset_txpa i reference current for transmit oscillator 9 gnd_txosc supply ground 10 tank+ i transmit oscillator tank circuit 11 tank- i transmit oscillator tank circuit 12 vcc_div supply divider section supply voltage 13 gnd_osc supply ground 14 mod_cntrl i modulus control input 15 div_out+ o divider output positive 16 div_out- o divider output negative 17 ratio_sel i ratio select 18 gnd_div supply ground divider section 19 txosc+ o transmit oscillator monitor output positive 20 txosc- o transmit oscillator monitor output negative 21 vcc_txosc supply transmit oscillator supply voltage 22 gnd_rx supply ground 23 rxvcoin i input buffer for 1ghz vco signal from ace9010 24 n.c. - no connection 25 vcc_rx supply receiver section supply voltage 26 n.c. - no connection 27 n.c. - no connection 28 vcc supply on/off logic supply voltage pin connections characteristic min typ max unit supply currents sleep pd1 = 0, pd2 = 0 0.11 ma standby pd1 = 1, pd2 = 0 6 8 ma transmit set up pd1 = 0, pd2 = 1 36 51 ma duplex pd1 = 1, pd2 = 1 48 63 ma input levels pd1, pd2 high 1.9 3.1 v pd1, pd2 low 0 0.5 v mod cntrl high vcc/2 + 0.3 vcc v mod cntrl low 0 vcc/2 - 0.3 v ratio sel high 0.6vcc vcc v ratio sel low 0 0.4vcc v input currents pd1, pd2 high 40 a pd1, pd2 low -0.1 0.1 a dc characteristics electrical characteristics these characteristics apply over these ranges of conditions (unless otherwise stated): t amb = e 30 c to + 85 c, v cc = 3.75 0.15v or 4.85 0.15v (see fig. 3 for test circuit).
2 ace9020 notes: 1. exceptions. harmonics of divider output -37dbc max applicable when fvco = 975.1354 mhz ratio = 65 10th harmonic of faux -47dbc applicable when faux = 90mhz, fvco = 989.9375mhz 2. residual modulation referenced to a 1khz signal giving 3khz deviation. measured with 750 s de-emphasis and ccitt filter. characteristic min typ max unit txosc output differential output 500 mv p-p txosc frequency 70 140 mhz frequency / supply sensitivity 75 khz spurii > 700mhz -40 dbc differential output capacitance 2 pf external tank inductance f = 90mhz 82 100 nh external tank inductance f = 122.5mhz 56 68 nh power up time (from standby) 65 s txpa output signal output power (rl = 50 ) 036dbm noise at f = +/- 45 mhz -145 dbc/hz noise at f = +/- 25 khz -100 dbc/hz harmonic content -20 dbc spurious - image -10 dbc spurious (fvco 2faux) -30 dbc spurious (fvco 3faux) -25 dbc spurious ( f = 45mhz 15 khz) except 2fvco - 9faux -105 dbc spurious 2fvco - 9faux -60 dbc spurii within 800 to 940 mhz (note1) -70 dbc other spurii except image -30 dbc isolation txpa off (pd2 = pd1 = 1) 55 db power up time 25 s isolation txpa to rvcoin 45 db residual modulation (note 2) -40 db rvcoin input signal signal level -10 dbm input impedance 50 divider input frequency 800 1100 mhz upconverter input frequency 910 1040 mhz phase noise f = 45mhz -155 dbc/hz phase noise f = 25khz -117 dbc/hz spurious - harmonic -20 dbc spurious - non-harmonic -80 dbc divider differential output level 500 600 mv p-p output rise / fall time 15 ns mod control set up time 20 ns mod control hold time 1ns ac characteristics electrical characteristics these characteristics apply over these ranges of conditions (unless otherwise stated): t amb = -30 c to + 85 c, v cc = 3.75 0.15v or v cc 4.85 0.15v (see fig. 3 for test circuit).
4 ace9020 figure 3 - ace9020 test circuit description the ace9020 is designed for use in a transceiver such as an analog cellular phone, which uses an offset modulation transmit architecture. the circuit consists of a vhf voltage controlled oscillator to generate the offset frequency, an upconverter to transmit frequency and also a prescaler for the main uhf phase locked loop. the rxvcoin signal to the ace9020 is normally the uhf local oscillator used for downconversion. a basic block diagram is shown in fig. 2, further information on external connections is provided in the test circuit (fig. 3) and the applications diagram (fig. 4). vhf oscillator this oscillator is a differential design which uses an external tank circuit as shown in fig. 3 and fig. 4. the components shown in fig. 3 give a vco frequency of 90mhz. a varactor diode is coupled capacitively to the tank circuit; the anode is referenced to ground via a resistor. the vco control from a synthesiser (eg ace9030) charge pump output is applied to the cathode of the varactor also through a resistor. these resistors should be the same value to keep the differential circuit balanced. the vco gain with the components shown will be typically 2 mhz/v. modulation is applied to the anode via a resistive divider as shown in fig. 4; the actual signal applied to the varactor will be small as the frequency deviation will typically be a maximum of 12khz in many applications. differential buffered outputs from the oscillator (txosc) interface directly to the ace9030 auxiliary synthesier inputs. upconverter an image reject mixer is used for the upconversion. this provides typically 20db rejection of the unwanted upper sideband. the quadrature networks for the mixer are all provided on chip; this is optimised for uhf local oscillator and vhf offset oscillator frequencies typically used for analog cellular phones on the amps and tacs systems. further filtering of the txpa output will be required to provide further suppression of the unwanted upper sideband, local oscillator signal and harmonics to meet cellular telephone specifications. saw filters are available for the various transmit frequency bands. the upconverter outputs (txpa + and -) are differential current outputs. the use of differential outputs minimises current switching within the device and thus minimise cross- talk to other circuit blocks. the txpa outputs must be matched to the external filter, normally 50 and single-ended. the network shown in fig. 3 provides a transformation from 400 differential to 50 single-ended and also provides dc bias from the vcc supply to the open collector txpa outputs. this network provides plus and minus 90 phase shift in each output which are then summed. alternatively a balun transformer could be used, it will again be necessary to provide dc bias to the txpa outputs. the load to the current outputs should be maximised to obtain the maximum power output; 400 is an optimum figure as higher values require impractical component values for matching. prescaler the two modulus prescaler is part of the uhf phase locked loop. it will typically be operating with ace9030 radio interface and synthesiser. there is also a choice of divider ratio, set by the ratio select input as shown in table. 1, below. the differential divider outputs can be directly coupled to the ace9030 main synthesiser inputs. ace9020 rxvcoin 22k 18k vcc vcc vco control txosc div out + - + - + txpa - 27n 27n 18n 1p 27p 1p tx output 100p 100p 18p 100n bb545 6k8 6k8 5,12,21,25,28 10 11 23 48 3,9,13, 18,22 16 15 19 20 6 7 mod cntrl ratio sel 14 17 pd1 12 pd2 faux = 90 mhz ratio sel ratio sel = low = high mod_cntrl = low 129 65 mod_cntrl = high 128 64 table 1
4 ace9020 power control circuits the inputs pd1 and pd2 are used to select the operating modes as shown below: pd1 pd2 mode 0 0 sleep all circuits off 1 0 standby prescaler on 1 1 transmit set up prescaler, vhf oscillator on. upconverter off 0 1 duplex all circuits on the power down inputs (pd1, pd2) are compatible with ace9030 digital outputs (do5, 6, 7). these modes allow circuit operation and power consumption to be optimised. the ace9020 can be put in sleep mode (0, 0) when the power consumption is minimal. the standby mode (1, 0) is used when the phone is in standby (receive only). the prescaler is operational to maintain the main uhf pll; all circuitry associated with transmit functions is turned off. there is an intermediate transmit set up state (1, 1). this allows the vhf oscillator and phase locked loop to stabilise before enabling the upconverter, preventing spurious transmissions. the time required for this state will be determined primarily by the vhf pll settling time. the power down inputs can then be set to (0, 1) the full duplex condition. the intermediate state should also be used during a ?handoff? during conversation on an analogue cellular phone, the vhf pll continuing to operate while the main uhf pll changes channel, the transmit output being disabled. it is also recommended that the intermediate state is used when going from duplex (0, 1) to standby (1, 0) modes. operating notes good rf layout techniques should be used for this device to obtain optimum performance and also minimise crosstalk between circuit blocks. rf supply decoupling should be provided adjacent to vcc pins; a value of 27pf is recommended. two external bias resistors are required. a 22k resistor is connected from bias ref (pin 4) to ground. this sets an accurate reference current for the chip. an 18k resistor is connected from rset txpa (pin 8) to ground which controls the output level of the vhf oscillator and hence the txpa output level. figure 4 - application diagram
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